Microchip’s new 23K256 is a serially interfaced 32 kilobyte SRAM memory chip, offered in 8 pin DIP as well as 8 pin SO packages. SRAM, like EEPROM, is a data storage medium. data kept in SRAM is lost without constant power, however it’s truly quick as well as there’s no limits to the number of compose cycles. EERPOM stores data even without power, however it’s sluggish as well as typically restricted to around a million compose cycles.
32K SRAM chips normally have 15 address lines as well as 8 data lines, like the IS61LV256AL we utilized on our CPLD advancement board. The 23K256 needs just four signal lines, however sacrifices the speed of a parallel memory interface. It’s a excellent method to add additional memory to a low-pin count microcontroller without routing 23 signal traces. We’ll show you exactly how to interface this chip below.
Microchip 23K256, 32K SPI SRAM (Mouser search, Octopart search, $1.48). Datasheet (PDF).
Bus Pirate
23K256 (pin #)
CS
/CS (1)
MISO
SO (2)
MOSI
SI (5)
Clock
SCK (6)
GND
/HOLD (7)
GND
VSS (4)
+3volts
VCC (8)
We linked the 23K256 to our Bus Pirate universal serial interface tool as shown in the table. It’s extremely essential to power the chip utilizing only the Bus Pirate’s 3.3volt supply, the 23K256 isn’t rated for 5volts.
The Bus Pirate is an simple method to discover about a chip without composing any type of code, however the exact same principals apply to utilizing the 23K256 with any type of microcontroller. This presentation utilizes the latest version of the Bus Pirate firmware (26-FEB-2009), which you can download from our Google Code SVN.
HiZ>m <–choose mode 1. HiZ … 5. SPI … MODE>5 <–SPI mode MODE SET … <–30KHz, all default settings SPI READY SPI>W <–capital ‘W’ allows power supplies VOLTAGE supplies ON SPI>
First, we put the Bus Pirate into SPI mode at 30KHz as well as selected the default settings for all options. We enabled the Bus Pirate’s on-board 3.3volt power supply with a funding ‘W’.
Configuration register
bit 7,6 = byte (00) page (10) sequence (01) mode
bit 0 = Hold disabled (1)
Data is kept inside the 23K256 in 1024 pages that each include 32bytes. The range of reads as well as composes is set by bit 7 as well as 6 of the configuration register. storage can be accessed by the byte (00), by 32byte pages (10), or sequentially with the entire 32K (01). We’ll work in sequence mode, which provides us gain access to to checked out as well as compose any type of length of data, anywhere in the 32K of storage space.
The hold pin is utilized to pause transfers when other chips on the exact same bus requirement to be accessed. bit 0 of the configuration register controls the hold pin. When set to 1, the hold pin is disabled. We connected hold to ground for typical operation, however its performance can be totally disabled by setting bit 0.
The configuration register is altered by sending the compose configuration command (0b00000001) as well as the new settings.
SPI>[0b1 0b01000001] <–update config register CS ENABLED WRITE: 0x01 <–write config command WRITE: 0x41 <–value to write CS DISABLED SPI>
We begin an SPI deal by enabling the 23K256 chip choose line ([). We send the compose configuration command (0b1, 0x01, or 1), complied with by the new settings for the configuration register (0b01000001, 0x41). We set bit 6 for sequential gain access to mode, as well as set bit 0 to disable the hold pin function. bits 5-1 have no function, however the datasheet states to always compose 0. The deal concludes by disabling the chip choose signal (]).
SPI>[0b101 r]
CS ENABLED
WRITE: 0x05 <–read config register
READ: 0x41 <–value read
CS DISABLED
SPI>
Next, we utilize the checked out configuration register command (0b00000101, 0b101, 0x05, or 5) to confirm that the settings were correctly written. This command returns one byte (r) which ought to match the value we composed in the previous operation (0x41, or 0b01000001).
Data access
Now we can checked out as well as compose data to the chip. composes begin with the data compose command (0b10, 0x02, or 2), complied with by two bytes which identify where to compose the data. The values to store are sent after the address. depending upon the gain access to mode, a single byte, a page, or the entire memory can be filled in a single operation.
SPI>[0b10 0 0 1 2 3 4 5 6 7 8 9 10]
CS ENABLED
WRITE: 0x02 <–data compose command
WRITE: 0x00 <–address byte 1
WRITE: 0x00 <–address byte 2
WRITE: 0x01 <–start of data to write
WRITE: 0x02
WRITE: 0x03
WRITE: 0x04
WRITE: 0x05
WRITE: 0x06
WRITE: 0x07
WRITE: 0x08
WRITE: 0x09
WRITE: 0x0A
CS DISABLED
SPI>
We begin with the compose data command (0b10) as well as set the compose place to the beginning of the chip (0 0). We send a overall of ten values to store, the numbers 1 to 10.
After composing the data, we can checked out it back with the checked out data command (0b00000011, 0b11, 0x03, or 3).
SPI>[ 0b11 0 0 r:10]
CSENABLED
WRITE: 0x03 <–read data command
WRITE: 0x00 <–start address byte 1
WRITE: 0x00 <–start address byte 2
BULK checked out 0x0A BYTES: <–read out 10 bytes
0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A
CS DISABLED
SPI>
We send the checked out data command (0b11), complied with by the address from which to begin reading (0 0). We then checked out back 10 bytes (r:10). The 10 byte are the numbers 1 to 10, the exact same values we composed in the previous step.
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